Intro for Controls of Motion Control LSI


Topics:

The motion control LSIs from Nippon Pulse Motor includes the PCD4600 series: ideal LSIs for stepping motor control, the PCD2100 series: a compact size LSI capable of controlling both stepping and servo motors, the PCL6100 series: the cost-effective LSIs which can support servo motors, and the PCL6000 series: high-end LSIs providing excellent functionality. In this section, we will focus on the PCL6100 series LSIs and explain their control methods.

The PCL6100 series includes three models: Single-axis control (PCL6115), 2-axis control (PCL6125), and 4-axis control (PCL6145).

Connection between Pulse Control LSIs and CPUs (1):  Parallel Bus

Key features include: the maximum output frequency of 15Mpps, 32-bit up-down counters, and the linear interpolation functionality. The CPU interface supports 8 and 16-bit parallel buses and 4-wire serial buses (SPI: serial peripheral interface).

Pulse Control LSIs (hereafter referred to as PCL) are connected to the host CPU via a parallel or serial bus, receiving commands from the CPU to control the motor movements.

Example 1...Motorola 68000 type CPU: 16-bit data bus

The procedure is more complex than the Intel method in the next section, but it is more reliable.

Control signals include R/#W signal, #LDS (Data Strobe) signal, and #DTACK (Data Acknowledge) signal (Figure 1). The R/#W signal is in read mode at H-level and write mode at L-level.

Example 2...Intel 8086 type CPU: 16-bit data bus

The Intel 8086 type control method includes control signals #RD (Read) and #WR (Write) (Figure 4). Reading occurs when #RD = L-level (CPU ← Memory) (Figure 5), and writing occurs when #WR changes from L-level to H-level (CPU → Memory) (Figure 6).

Examples of data writing/reading on Parallel Bus

The address map of PCL6145 is shown (Table 2). Note that the single-axis LSI, PCL6115 has an address map only for X-axis, and the dual-axis LSI, PCL6125 has an address map only for X-axis and Y-axis.

Connection between Pulse Control LSIs and CPUs (2): Serial Bus

The 4-wire synchronous serial bus, SPI (serial peripheral interface) is adopted. 

The PCL61x5 series can control up to four sub-node LSIs with a single select signal (SS) from the Main (assuming the CPU here).

The sub-node LSI is identified by the setting status of SN0 and SN1 pins and the "device selection" data written to MOSI (Figure 8).

Examples of data writing/reading on Serial Bus

The example below shows the pulse control LSI PCL61x5 via serial bus.

Operation procedures of Pulse Control LSIs

When operating the Pulse Control LSI (PCL), follow the steps in Figure 10.

Example of PCL controls...Creating Linear Acceleration/Deceleration operations

The following explains a setting example for linear acceleration/deceleration operation shown in Figure 11. Table 12 shows the settings of each register.

Pre-registers and Registers

PCL has models with Pre-registers and Registers. WE will explain the functions using PCL61x5 as an example (Table 20).


Next Section